Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry

ABSTRACT

Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

TECHNICAL FIELD

This invention relates to semiconductor processing methods of formingcontact openings, methods of forming electrical connections andinterconnections, and integrated circuitry comprising such contactopenings and electrical connections and interconnections.

BACKGROUND OF THE INVENTION

Referring to FIGS. 1 and 2, a semiconductor wafer fragment is indicatedgenerally at 10 and comprises a semiconductive substrate 12. In thecontext of this document, the term “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above. Substrate 12 comprises afield oxide region 13 having an outer surface 14 (FIG. 2) over which aplurality of conductive runners or conductive lines 16, 18, and 20 areformed. The illustrated conductive lines or runners include conductiveportions and insulative portions. Exemplary conductive portions areconstituted, in this example, by a respective polysilicon layer 22 andan overlying suicide layer 24. The insulative portions of the runners orlines are constituted by respective overlying caps 26 and associatedsidewall spacers 28. Exemplary materials for the insulative portionsinclude oxides and nitrides.

An insulative layer 30 such as borophosphosilicate glass is formed overrunners 16, 18, and 20 and a contact opening 32 is formed through amasked etch of layer 30 to outwardly expose a portion of silicide layer24. Thereafter, conductive material such as conductively dopedpolysilicon is formed within contact opening 32 to provide a conductivecontact 34 to conductive line 18. A metal layer 36 is provided thereoverto form an electrical connection with conductive line 18.

A typical practice within the semiconductor industry is to provide aconductive line or runner with a widened landing pad in order toaccommodate mask misalignments when contact openings are formed. Anexemplary widened landing pad is shown in FIGS. 1 and 2 at 38. By havinga widened landing pad, contact opening 32 can shift left or right somedistance relative to the position shown in FIGS. 1 and 2 without makingundesirable contact with the substrate. For purposes of the ongoingdiscussion, landing pad 38 includes the conductive and insulativeportions of conductive line 18; and the conductive portions ofconductive line 18 define a contact pad with which electricalcommunication is desired. Accordingly in the illustrated example acontact pad is defined by polysilicon layer 22 and silicide layer 24 ofconductive line 18. The contact pad defines a target area A inside ofwhich it is desirable to form a contact opening. An electricalconnection through contact opening 32 can be formed anywhere withintarget area A and still effectively make a desirable connection with theconductive contact pad. Hence, the target area tolerates a contactopening mask misalignment on either side of the illustrated and desiredcontact opening 32. A tradeoff for improved mask misalignment toleranceis a reduction in wafer real estate available for supporting conductivelines and other integrated circuitry components. This is due largely inpart to the increased area which is occupied by the widened landing pad38. This also adversely impacts the conductive line spacing such thatdesired minimum spacing adjacent conductive lines is not achieved.Hence, integrated circuitry cannot be packed as densely upon a wafer asis desirable when the widened landing pads are used.

This invention grew out of concerns associated with enhancing theefficiency with which wafer real estate is used to support integratedcircuitry. This invention also grew out of concerns associated withimproving the methods and structures through which contact is maderelative to conductive lines.

SUMMARY OF THE INVENTION

Methods of forming contact openings, making electrical interconnections,and related integrated circuitry are described. Integrated circuitryformed through one or more of the inventive methodologies is alsodescribed. In one implementation, a conductive runner or line having acontact pad with which electrical communication is desired is formedover a substrate outer surface. A conductive plug is formed laterallyproximate the contact pad and together therewith defines an effectivelywidened contact pad. Conductive material is formed within a contactopening which is received within insulative material over theeffectively widened contact pad. In a preferred implementation, a pairof conductive plugs are formed on either side of the contact padlaterally proximate thereof. The conductive plug(s) can extend away fromthe substrate outer surface a distance which is greater or less than aconductive line height of a conductive line adjacent which the plug isformed. In the former instance and in accordance with one aspect, suchplug(s) can include a portion which overlaps with the contact pad of theassociated conductive line.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a top plan view of a prior art semiconductor wafer fragmentand a plurality of conductive lines supported thereon.

FIG. 2 is a view which is taken along line 2-2 in FIG. 1 at a subsequentprocessing step.

FIG. 3 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with one implementation ofthe invention.

FIG. 4 is a view of the FIG. 3 wafer fragment at another processingstep.

FIG. 5 is a view of the FIG. 3 wafer fragment at another processingstep.

FIG. 6 is a view of the FIG. 3 wafer fragment at another processingstep.

FIG. 7 is a view which is similar to the FIG. 6 view, but which shows analternate embodiment in accordance with another implementation of theinvention.

FIG. 8 is a view of the FIG. 3 wafer fragment at another processingstep.

FIGS. 9 and 10 are top plan views of semiconductor wafer fragments whichhave been processed in accordance with the inventive methodologies.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

Referring to FIG. 3, like numerals from the above-described embodimentare utilized where appropriate, with differences being indicated by thesuffix “a” or with different numerals. Accordingly, a plurality ofconductive runners or lines 16 a, 18 a, and 20 a are formed over outersurface 14, and can be formed over oxide isolation regions 40. Exemplaryisolation regions include shallow trench isolation regions or fieldoxide regions formed through LOCOS techniques. The conductive linescomprise respective outermost surfaces 44 portions of which definerespective conductive line heights h outwardly of outer surface 14.Diffusion regions 42 can be provided between the conductive lines, andpreferably comprise n- regions having doping concentrations of 1×10¹⁸cm⁻³. The diffusion regions can be provided in a separate doping step,or through outdiffusion of dopant from conductive material which willbecome more apparent below. An outer contact opening target area B isdefined by conductive line 18 a.

Referring to FIG. 4, an insulating material layer 46 is formed oversubstrate 12. An exemplary material is borophosphosilicate glass.

Referring to FIG. 5, at least one, and preferably a pair of contactopenings 48, 50 are formed through layer 46 and preferably outwardlyexpose respective portions of outer surface 14. The contact openings canbe formed through a suitable masked etch of layer 46. Preferably, theindividual contact openings are essentially self-aligned at and to thesubstrate at two locations 48 a, 48 b, and 50 a, 50 b respectively,along a line extending laterally from conductive runner or line 18 a. Ina preferred implementation, one of the two locations for the individualcontact openings is defined by conductive runner 18 a. Even morepreferably, the other of the two respective locations are defined byrespective next adjacent conductive lines 16 a, 20 a.

Referring to FIG. 6, and in accordance with a first implementation,first conductive material 52, 54 is formed within contact openings 48,50, between the illustrated conductive lines and laterally proximate oradjacent the contact pad defined by conductive line 18 a. An exemplaryand preferred first conductive material is conductively dopedpolysilicon, which can serve as a source of outdiffused dopant forregions 42. The polysilicon can be chemical vapor deposited over thesubstrate and subsequently removed through conventional processing toprovide conductive plugs 56, 58. Such conventional processing caninclude planarization processing to isolate conductive material withinthe respective contact openings, followed by a suitable timed etch torecess the conductive material within the contact openings. In theillustrated example, conductive plugs are formed on both sides ofconductive line 18 a. It is possible, however, for only one conductiveplug to be formed on either side of conductive line 18 a. The individualconductive plugs are essentially self-aligned at and to the substrate atthe same locations as are the contact openings in which each is formed.

Referring still to FIG. 6, the illustrated conductive plugs are formedto preferably extend outwardly from outer surface 14 a distance which isgreater than conductive runner height h. Because the plugs in thisexample are formed atop the same surface (outer surface 14) atop whichthe conductive lines are formed, each extends elevationally beyond therespective conductive line heights. Such plugs could, however, be formedto extend from outer surface 14 a distance which is less than or nofurther than the conductive runner height. This could, for example, bedone by conducting a timed etch for a longer period of time than issuitable for forming the illustrated FIG. 6 plugs. An exemplaryconstruction is shown in FIG. 7.

In one implementation, individual conductive plugs include portionswhich overlap with portions of conductive line 18 a and the respectivenext adjacent conductive lines 16 a, 20 a. In a preferredimplementation, the respective plugs overlap with the outermost surfacesof the conductive lines adjacent which each is formed. Accordingly,portions of at least one, and preferably both conductive plugs canoverlap target area B. Collectively, the conductive material ofconductive plugs 56, 58, and the conductive material of conductive line18 a define an effective contact pad having an outermost surface 60,which defines an effectively widened target area A′. The widened targetarea reduces the wafer area which was formerly required by the prior artwidened landing pad (FIGS. 1 and 2) described above.

Alternately considered, effective contact pad outermost surface 60defines a generally non-planar surface. In a preferred implementation,at least one of the conductive plugs, and preferably both, define aregion of outermost surface 60 having a higher topographical elevationthan the region defined by the contact pad of line 18 a.

Referring to FIG. 8, a layer 62 of insulative material is formed overthe substrate and the effective contact pad. A contact opening 64 isetched or otherwise formed through layer 62 to outwardly expose portionsof the effective contact pad. Preferably, the contact pad of line 18 ais exposed, with any mask misalignment resulting in exposure ofconductive material of either or both of conductive plugs 56, 58.Subsequently, a second conductive material 66 is formed within contactopening 64 and in electrical communication with at least portions of thecontact pad and, if exposed, an associated portion of a conductive plug.A bit line 68 can then be formed over the substrate and in electricalcommunication with material 66.

Referring to FIG. 9, conductive lines 16 a, 18 a and 20 a have firstrespective line widths w₁ at respective first locations and second linewidths w₂ at respective second locations, an exemplary second line widthand location being shown for line 18 a. The second line widthcorresponds to a line location where at least a portion of contactopening 64 is formed. In one implementation, the first and second linewidths are essentially the same or equivalent. This is made possiblebecause the above-described conductive plugs 56, 58 (shown in dashedlines in FIGS. 9 and 10) reduce, if not eliminate, the requirement ofthe FIG. 1 widened landing pad. The illustrated conductive plugs providean effective contact pad width which is greater than second line widthw₂, and include respective portions proximate the first line width w₁which overlap with or extend elevationally over the conductive portions,e.g. the contact pad, of line 18 a. The plugs can also include portionswhich overlap with corresponding portions of conductive lines 16 a, 20a. This compensates for a contact opening mask misalignment by enablingdesired contact to be made through a respective one of the conductiveplugs as discussed above.

Referring to FIG. 10 and in accordance with another implementation,localized first and second line widths w₁, w₂ respectively, aredifferent with second line width w₂ being greater than first line widthw₁. In this example, the second line width defines a portion of alanding pad which is smaller in dimension than the FIG. 1 landing pad.Portions of conductive lines 16 b and 20 b laterally proximaterespective conductive plugs 56, 58 can be tapered or otherwiseconfigured to accommodate the somewhat wider landing pad.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-51. (canceled)
 52. Integrated circuitry comprising: a semiconductivesubstrate having an outer surface; a conductive line disposed over theouter surface and having a conductive portion which defines a contactpad with which electrical connection is desired; at least one conductiveplug disposed laterally proximate the contact pad and having a plugportion disposed elevationally over a portion of the contact pad; andconductive material disposed over the contact pad and in electricalcommunication with at least a portion of the conductive plug. 53.Integrated circuitry comprising: a semiconductive substrate having anouter surface; a conductive line disposed over the outer surface andhaving a first line width at one location and a second line width whichis different from the first line width at another location; at least aportion of the second line width defining a contact pad with whichelectrical connection is desired; a conductive plug disposed laterallyproximate the contact pad and defining therewith an effective contactpad having an effective contact pad width which is greater than thesecond line width; and conductive material disposed over the effectivecontact pad and making electrical connection with at least a portion ofthe conductive plug.
 54. Integrated circuitry comprising: asemiconductive substrate having an outer surface; a conductive linedisposed over the outer surface and having a conductive line width and atarget area with which electrical communication is desired; a pair ofconductive plugs disposed over the outer surface on either side of theconductive line laterally proximate the target area and self-aligned tothe substrate adjacent the conductive line, the plugs and target areadefining an effectively widened target area; and conductive materialdisposed over and in electrical communication with at least a portion ofthe effectively widened target area which includes the conductive linetarget area.
 55. Integrated circuitry comprising: a semiconductivesubstrate having an outer surface; a first and second conductive runnercomprising polysilicon disposed over the outer surface; a contact padcomprising part of the first conductive runner; and a conductive plugcomprising polysilicon disposed over the outer surface laterallyproximate and between the contact pad and the second conductive runner,the conductive plug being essentially self-aligned at and to thesemiconductive substrate at two locations, one of the two locationsbeing defined by the second conductive runner.
 56. The integratedcircuitry of claim 55, wherein: the first conductive runner comprises anoutermost surface which defines a conductive runner height; and theconductive plug extends away from the substrate outer surface a distancewhich is greater than the first conductive runner height.
 57. Theintegrated circuitry of claim 56, wherein the conductive plug comprisesa portion which overlaps with the conductive runner's outermost surface.58. The integrated circuitry of claim 56, further comprising: a thirdconductive runner disposed over the outer surface adjacent the firstconductive runner; and a second conductive plug disposed over the outersurface laterally proximate and between the contact pad and the thirdconductive runner, the conductive plug being essentially self-aligned atand to the semiconductive substrate at two locations, one of the twolocations being defined by the third conductive runner.
 59. Theintegrated circuitry of claim 58, wherein the second conductive plugextends away from the substrate outer surface a distance which isgreater than the first conductive runner height.
 60. The integratedcircuitry of claim 58, wherein the second conductive plug comprises aportion which overlaps with the conductive runner's outermost surface.